Graded Channel and Multiple-Gate Devices in SOI Technology for Analog and RF Applications


First Edition

The objective of this research is to study the feasibility of the various fabrication process for this GAA device, to analyse the electrical characteristics of these devices from DC characteristics up to 110 GHz and to describe their... Read More

The motivation to study this non-classical CMOS device is necessary to face with the ITRS constraints. In the ITRS roadmap, the gate length of devices are being scaled down rapidly but this rapid scaling is not in pace with the relatively slow scaling of the gate equivalent oxide thickness which leads to a degradation in the performance of the transistor. One of the solutions to this problem is the use of non-classical devices, such as the Gate-All-Around (GAA) MOSFET. Owing to the flexibility of SOI technology, these novel devices can be adapted to this technology bringing along with it the benefit of SOI technology. One of the main advantage of building this GAA device on SOI technology is that it offers the possibility whereby the second gate is easily built into the back of the device. The objective of this research can be divided into three parts; the first is to study the feasibility of the various fabrication process for this GAA device, the second to analyse the electrical characteristics of these fabricated GAA devices from DC characteristics up to 110 GHz and the third one is the use of commercial numerical simulation softwares (IE3D, Silvaco) in order to describe the physics of these novel devices. In this study, these different structures shows advantages and disadvantages when used in either analog or RF applications. The graded-channel structure has shown that it is advantageous when used in high performance analog circuits. The advantages of this structure is further enhanced when it is combined with the double-gate structure, forming a double-gate graded channel SOI MOSFET. Optimizing in terms of doping level along the channel of the graded-channel is important to yield good electrical results. In order for these devices to be successful commercially, it is important that they are compatible with the fabrication technology and trends available today and in the near future. To confirm that these devices can be adapted into today's and tomorrow's technology, we have shown that these they are easily adaptable in the current technology. Multiple-gate devices are a new group of devices which have been identified by ITRS as potential devices to meet the demands in the future. In this study, we have shown that these multiple-gate devices do indeed show improved short-channel effects and improved analog and RF characteristics when compared to the single-gate devices in existence.


Paperback - In English 21.89 €

Specifications


Publisher
Presses universitaires de Louvain
Title Part
Numéro 146
Author
Tsung Ming Chung,
Collection
Thèses de l'École polytechnique de Louvain
Language
English
Publisher Category
Economics and Social Sciences > Communication and media > Information and Communication Technologies
Publisher Category
Economics and Social Sciences > Communication and media
Publisher Category
Applied Sciences
BISAC Subject Heading
TEC000000 TECHNOLOGY & ENGINEERING
Onix Audience Codes
06 Professional and scholarly
CLIL (Version 2013-2019)
3069 TECHNIQUES ET SCIENCES APPLIQUEES
Title First Published
01 January 2007
Type of Work
Thesis

Paperback


Product Detail
1 A4
Publication Date
01 January 2007
ISBN-13
9782874630682
Extent
Main content page count : 264
Code
75708
Dimensions
16 x 24 x 1.5 cm
Weight
434 grams
List Price
21.89 €
ONIX XML
Version 2.1, Version 3

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Contents


List of Figures xvii

List of Tables xxvii

List of Abbreviations xxxi

List of Symbols xxxiii

1 Introduction 1

1.1 History . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Timeline of Semiconductor Devices . . . . . . . . . . 1

1.3 Development of SOI MOSFET's . . . . . . . . . . . . 2

1.4 Why Novel Devices based on SOI Technology? . . . . 6

1.5 Multiple-gate devices . . . . . . . . . . . . . . . . . . 8

1.5.1 Introduction . . . . . . . . . . . . . . . . . . . 8

1.5.2 Why the move to multiple-gate devices? . . . . 12

1.5.3 Advantages of the multiple-gate structure . . . 13

1.5.3.1 Subthreshold Regime . . . . . . . . 13

1.5.3.2 Increased drain current . . . . . . . 15

1.5.3.3 Speed superiority . . . . . . . . . . 17

1.5.3.4 Volume inversion . . . . . . . . . . 17

1.6 PresentWork . . . . . . . . . . . . . . . . . . . . . . 19

2 Numerical simulation tools 27

2.1 Numerical simulations . . . . . . . . . . . . . . . . . 27

2.2 Monte-Carlo Simulation . . . . . . . . . . . . . . . . 28

2.3 Challenges and needs . . . . . . . . . . . . . . . . . . 28

2.4 Different numerical simulation tools . . . . . . . . . . 30

2.5 Numerical simulation: ATLAS Package . . . . . . . . 33

2.5.1 Theory of Carrier Statistics . . . . . . . . . . . 33

2.5.2 Transport model . . . . . . . . . . . . . . . . 34

2.5.2.1 Drift-diffusion model . . . . . . . . 35

2.5.2.2 Energy Balance model . . . . . . . . 36

2.5.3 Recombination and generation of carriers . . . 37

2.5.4 Impact Ionization . . . . . . . . . . . . . . . . 38

2.5.5 Interface charge . . . . . . . . . . . . . . . . . 41

2.5.6 Mobility . . . . . . . . . . . . . . . . . . . . 41

2.5.7 Self-heating . . . . . . . . . . . . . . . . . . . 42

2.5.8 Carrier heating . . . . . . . . . . . . . . . . . 43

2.6 Doping Profile . . . . . . . . . . . . . . . . . . . . . . 43

2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 45

3 Graded-Channel Single-Gate and Double-Gate SOI MOSFETs 47

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 47

3.2 Fabrication of Graded-Channel devices . . . . . . . . 50

3.3 Graded-Channel Single-Gate SOI MOSFET . . . . . . 54

3.3.1 Threshold voltage and Subthreshold-slope at Low- Vds . . . . . . . . . . . . . . . . . . . . . . . 55

3.3.2 Saturation Current . . . . . . . . . . . . . . . 57

3.3.3 Analog Characteristics . . . . . . . . . . . . . 59

3.4 Graded-Channel Double Gate devices . . . . . . . . . 63

3.4.1 Introduction . . . . . . . . . . . . . . . . . . . 63

3.4.2 Analytical Modeling . . . . . . . . . . . . . . 66

3.4.3 Subthreshold Regime . . . . . . . . . . . . . . 68

3.4.4 Saturation Current . . . . . . . . . . . . . . . 69

3.4.5 Analog characteristics . . . . . . . . . . . . . 73

3.4.5.1 Gate transconductance . . . . . . . . 73

3.4.5.2 Transconductance-to-current ratio . . 75

3.4.5.3 Early voltage . . . . . . . . . . . . . 76

3.4.5.4 Voltage gain . . . . . . . . . . . . . 79

3.4.6 Graded-Channel architecture: Physics . . . . . 82

3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 87

4 Planar Double-Gate SOI MOSFET with prepatterned cavities 89

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 89

4.2 Planar double-gate MOSFET fabrication techniques . . 90

4.2.1 Gate-All-Around by isotropic etch of buried oxide 90

4.2.2 CEA-LETI wafer bonding . . . . . . . . . . . 91

4.2.2.1 Non-self-aligned double-gate wafer bondingprocess . . . . . . . . . . . . . . 91

4.2.2.2 Self-aligned double-gate wafer bondingprocess . . . . . . . . . . . . . . 94

4.2.3 Double-gate devices fabricated based on the Siliconon- Nothing device . . . . . . . . . . . . . . . 96

4.3 Double-gate fabrication with prepatterned cavities and wafer bonding . . . . . . . . . . . . . . . . . . . . . . 97

4.4 Critical points . . . . . . . . . . . . . . . . . . . . . . 101

4.4.1 Surface activation . . . . . . . . . . . . . . . . 103

4.4.2 Annealing . . . . . . . . . . . . . . . . . . . . 112

4.4.3 Cleanliness . . . . . . . . . . . . . . . . . . . 114

4.4.4 TMAH etching . . . . . . . . . . . . . . . . . 114

4.4.5 Chemical vapor deposition of Polysilicon into buried cavities . . . . . . . . . . . . . . . . . 115

4.4.6 Alignment of top and bottom gates . . . . . . . 118

4.5 Electrical characterization of built planar DG MOSFETs 120

4.6 Silicon-on-Nothing . . . . . . . . . . . . . . . . . . . 125

4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 135

5 Quasi Double-Gate SOI MOSFET 137

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 137

5.2 Devices analyzed . . . . . . . . . . . . . . . . . . . . 140

5.3 Analog and Digital analysis . . . . . . . . . . . . . . . 142

5.3.1 Analysis of 30 nm Si thickness devices . . . . 142

5.3.2 Analysis of 20 nm Si thickness devices . . . . 149

5.4 Limitation of emulating a Quasi Double-gate . . . . . 155

5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . 161

6 Performance comparison of Multiple-gate MOS devices 165

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 165

6.2 Numerical simulations of Multiple-gate MOSFETs . . 166

6.2.1 Subthreshold static performance . . . . . . . . 169

6.2.2 Analog static Analysis . . . . . . . . . . . . . 170

6.2.3 AC Analysis . . . . . . . . . . . . . . . . . . 177

6.2.3.1 Intrinsic capacitances . . . . . . . . 178

6.2.3.2 Parasitic capacitiances . . . . . . . . 178

6.3 Experimental results: FinFETs . . . . . . . . . . . . . 184

6.3.1 FinFET architectures . . . . . . . . . . . . . . 184

6.3.2 Measured DC characteristics . . . . . . . . . . 186

6.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . 191

7 Conclusion 195

A Example of net list for 2-D Double-Gate SOI MOSFET numerical simulation 201

B Example of net list for a 3-D Double-Gate SOI MOSFET numerical simulation 207

Bibliography 212